1. Field of the Invention
The present invention is directed to the field of semiconductor processing, and, more particularly, to a method of forming metal interconnections on an integrated circuit device.
2. Description of the Related Art
There is a constant drive to reduce the channel length of transistors to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconducting substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections. Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnections must be made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of a plurality of conductive lines and conductive plugs formed in alternative layers of dielectric materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc.
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. One factor that affects the speed at which integrated circuit products operate is the speed at which electrical signals propagate through the device. Electrical signals travel within the device along the interconnected conductive iines and contacts. The greater the resistance of these lines and contacts, the slower the signals will propagate through the integrated circuit device, and the slower it will operate.
A great level of effort goes into sizing and routing this vast collection of interconnections in an effort to minimize the resistance of the contacts and lines in the device such that device performance, i.e., speed, is optimized or at least suitable for the design parameters of the particular product under consideration. However, as with most products that have to be fabricated, variations in the physical dimensions or size of the contact, as compared to those contemplated by the particular design, may occur due to a variety of factors inherent in manufacturing operations. For example, contacts, as actually manufactured, may vary from their design size due to under- or over-etching, or the dielectric layer in which they will be formed may be manufactured thinner or thicker than that anticipated by the design process.
Whatever the source, variations in the physical size of a contact can have a negative impact on device performance. For example, as contact size decreases, the resistance of the circuit coupled to that contact increases, since the resistance of the contact is inversely proportional to the size of the contact. Left unchecked, errors such as those described above can reduce the overall performance and operating speed of the integrated circuit product.
The present invention is directed to a method of manufacturing semiconductor device that minimizes or reduces some or all of the aforementioned problems.